This invention relates generally to semiconductor memory devices, and particularly to cross-point array architecture for magnetoresistive random access memory (MRAM) storage devices.
Semiconductor devices are used for integrated circuits in a wide variety of electrical and electronic applications, such as computers, cellular telephones, radios, and televisions. One particular type semiconductor device is a semiconductor storage device, such as random access memory (RAM) and flash memory. These semiconductor storage devices use an electrical charge to store information.
A recent development in semiconductor memory devices involves spin electronics, which combines traditional semiconductor technology and magnetism. Rather than using an electrical charge to indicate the presence of a binary xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d, the spin of an electron is used. An example of such a spin electronic device is a magnetoresistive random access memory (MRAM) storage device, which includes conductive lines positioned perpendicular to one another in different metal layers. The place where the conductive lines intersect is known as a cross-point. In between the perpendicular conductive lines is a magnetic stack. The magnetic stack is placed at the cross-point, sandwiched between the conductive lines.
An electrical current flowing through one of the conductive lines induces a magnetic field around the conductive line. The induced magnetic field can align (or orient) the alignment (or orientation) of magnetic dipoles in the magnetic stack. The right hand rule is a way to determine the direction of a magnetic field induced by a current flowing in a particular direction. The right hand rule is well understood by those of ordinary skill in the art of the present invention.
A different current flowing through the other conductive line induces another magnetic field and can realign the polarity of the magnetic field in the magnetic stack. Binary information, represented as a xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, is stored as different alignments of the magnetic dipoles in the magnetic stack. A current of sufficient strength flowing through one of the conductive lines is sufficient to destroy the contents of the magnetic stacks coupled to it. However, currents flowing through both conductive lines are required to selectively program a particular magnetic stack.
The alignment of the magnetic dipoles in the magnetic stack changes the electrical resistance of the magnetic stack. For example, if a binary xe2x80x9c0xe2x80x9d is stored in the magnetic stack, the resistance of the magnetic stack will be different from the resistance of the same magnetic stack if a binary xe2x80x9c1xe2x80x9d is stored in the magnetic stack. It is the resistance of the magnetic stack that is detected and determines the logical value stored therein.
It is preferable to use long runs of the conductive lines to maximize storage density. The long conductive lines permit larger storage arrays and minimizes area overhead for support logic and devices such as current drivers and sinks, switches, etc. However, long conductive lines result in significant parasitic effects such as capacitance, inductance, and resistance. By reducing parasitic effects, the following advantages may be realized: precise control of writing current, longer conductive lines, shielding of read lines, and reduced power consumption.
Because MRAM devices operate differently than traditional semiconductor memory devices, they introduce design and manufacturing challenges. A need has therefore arisen for a cross-point array architecture to reduce parasitic effects.
In one aspect, the present invention provides an architecture for a magnetoresistive random access memory (MRAM) storage cell comprising a magnetic tunnel junction (MTJ), a wordline and a bitline perpendicular to the wordline, sandwiching the MTJ at their intersection, a first conductive line running parallel to the wordline, electrically separated from the wordline by a dielectric layer and a second conductive line running parallel to the bitline, electrically separated from the bitline by another dielectric layer.
In another aspect, the present invention provides an architecture for a magnetoresistive random access memory (MRAM) memory array arranged in a cross-point array with a plurality of wordlines and bitlines, the memory array comprising a plurality of MRAM memory cells arranged in a cross-point array, each MRAM memory cell comprising: a magnetic tunnel junction (MTJ) comprising a first and second magnetic layers separated by a non-magnetic layer, a wordline and a bitline lying perpendicular to the wordline, sandwiching the MTJ at their intersection, a first conductive line running parallel to the wordline, electrically separated from the wordline by a first dielectric layer; and a second conductive line running parallel to the bitline, electrically separated from the bitline by a second dielectric layer; and wherein subsets of MRAM memory cells are grouped together and share a common wordline and subsets of MRAM memory cells are grouped together and share a common bitline.
The present invention provides a number of advantages. For example, use of a preferred embodiment of the present invention permits precise control of the currents used to align the magnetic dipoles of the magnetic stacks. Precise control of the currents is possible due to the reduction in the parasitic effects, which in turn, reduces signal loss.
Also, the present invention provides a longer overall length for the conductive lines used in reading and writing the magnetic stacks. The longer length conductive lines allow for larger memory arrays, which in turn results in memory cells with greater density.
Additionally, the shielding of the read conductive lines allow for lower read currents to be used. Along with increased noise immunity due to the shielding, shortening of the read access time and the read cycle time can be achieved. The lower read currents also result in reduced power consumption.
Also, the present invention permits shorter read and write times due to the electrically separated architectures allowing read and write currents to be simultaneously maintained on the respective conductive lines, rather than having to switch from a read current to a write current as in other non-electrically separated architectures.